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Mentor Graphics Launches New Test Technology to Dramatically Increase the Capacity of Semiconductor Test Equipment By Up to 10 Times
WILSONVILLE, Ore.--(BUSINESS WIRE)--Oct. 1, 2001--Mentor Graphics
Corporation (Nasdaq:MENT) today announced new patent pending
Design-for-Test (DFT) technology called Embedded Deterministic Test
(EDT(TM)) that extends the capacity of automatic test equipment (ATE)
for a significant reduction in the cost of semiconductor testing,
which can represent as much as 50 percent of manufacturing costs.
Mentor's first EDT product, TestKompress(TM), employs the new
compression technology that allows semiconductor manufacturers to
reduce the ATE memory and time requirements for testing ASIC, IC and
System-on-Chip (SoC) designs by up to 10 times. This reduction allows
manufacturers to maximize the utilization of state-of-the-art test
equipment without jeopardizing product quality and to reduce the cost
of future ATE purchases.
According to Prime Research Group, the semiconductor industry
spent $4.9 billion in 2000 on digital IC and SoC tester purchases. At
least 60 percent ($2.9 billion) of this investment was made to meet
the increased capacity requirements. The shift from 200mm to 300mm
wafers by most leading manufacturers and the use of new fault models
to detect failure mechanisms associated with deep sub-micron (DSM)
designs are expected to continue to drive the need for additional test
capacity.
``While the cost of semiconductor manufacturing continues to drop
sharply year after year, the cost of test has continued to rise due to
skyrocketing gate count, increasing complexity, larger wafer size and
changing process technology,'' said Walden C. Rhines, chairman and CEO
of Mentor Graphics. ``From a purely economic standpoint, the impact
that EDT technology will have on the semiconductor manufacturers in
terms of reduction in capital spending could make TestKompress one of
the most important product introductions by Mentor.''
Reducing ATE Expenses
By increasing the capacity of test equipment, manufacturers are
not required to purchase expensive ATE memory upgrades or use test
pattern reloads or multiple pass testing. Test data compression
results from the combination of embedding test logic and the new
deterministic test pattern generation algorithms. The test logic is
embedded at the interface between the scan chains and the tester pins
without changing the system logic. In addition, the tight coupling of
test logic and test pattern generation eliminates the need for test
point insertions and ``X''-bounding logic used with other DFT methods.
The volume of devices that can be tested in a manufacturing
facility is determined by the amount of test time available. Currently
scan testing is the largest and most rapidly growing obstacle to
production throughput and can often represent more than 50 percent of
the total test time. TestKompress solves this issue by reducing the
scan test by up to 10 times, which increases the volume of devices
tested per ATE by up to 80 percent. Therefore, using TestKompress on
designs can significantly increase the manufacturing test floor's
overall throughput.
``TestKompress decreased the test data volume by 10 times in our
evaluation and it may eliminate the need to increase ATE memory for
the next several years,'' said Yoshio Okamura, Department Manager,
Design Technology Development Division, Semiconductor and Integrated
Circuits, Hitachi, Ltd. ``In addition the scan test time was
significantly reduced.''
Integration into DFT environments
TestKompress is fully compatible with time-proven scan and
automatic test pattern generation (ATPG) design-for-test flows.
TestKompress uses the same scan DFT methods, script files and ATPG
libraries as Mentor's FastScan(TM) product. The solution also supports
all scan methodologies and fault models. Additionally, TestKompress
uses the same test vector formats and tester interfaces enabling
seamless and intuitive ATE integration and adoption for users.
``Our test patterns were created and verified without impacting my
team's design schedule,'' stated Jun Qian, Design-for-Test manager,
Cisco Systems. ``My designers were able to use the EDT technology after
only one day of training.''
Pricing and Availability
The TestKompress product is immediately available in two versions:
The TestKompress 5X product provides users with compression benefits
up to five times and TestKompress 10X reduces the test data and test
time by up to 10 times. Both products are available under term
licenses with pricing beginning at approximately $2 million. For more
information regarding the TestKompress product line and the complete
portfolio of Mentor Graphics® ATPG, built-in self test (BIST) and
scan products, please visit the Mentor Graphics DFT Web site at
www.mentor.com/dft or email dft_info@mentor.com.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of more
than $600 million and employs approximately 2,975 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: www.mentor.com.
Mentor Graphics is a registered trademark and EDT, TestKompress
and FastScan are trademarks of Mentor Graphics Corporation. All other
company or product names are the registered trademarks or trademarks
of their respective owners.
Contact:
Mentor Graphics
Leanne White, 503/685-1984
leanne_white@mentor.com
or
Benjamin Group/BSMG Worldwide
Jason Khoury, 415/352-2628 ext. 172
jkhoury@bsmg.com
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